The present invention relates to analog to digital conversion, and, more particularly, is directed to a delta sigma type of analog to digital converter.
Delta sigma converters, also referred to as sigma delta modulators, convert a signal amplitude into digital data. An input signal at a given frequency f.sub.0 is oversampled, that is, sampled at a rate f.sub.s much higher than the Nyquist rate, f.sub.s &gt;&gt;2f.sub.0. When the delta sigma converter employs one-bit quantization, the output signal comprises a one-bit data pulse stream having a time average amplitude proportional to the amplitude of the input signal.
Quantization of the input signal introduces errors, that is, noise, into the output signal. A major advantage of delta sigma converters is their ability to shape the quantization noise spectrum, specifically, to move the noise from low frequencies into high frequencies. The output data is then low pass filtered to remove the noise.
A single bit first order delta sigma converter is shown in FIG. 1 as including subtractor 20, integrator 30, analog-to-digital converter 40 comprising comparator 43 and latch 46, and digital to analog converter 50.
An input signal S.sub.IN having a maximum frequency f.sub.0 is applied to an input terminal 10 which supplies the signal S.sub.IN to a subtractor 20. The subtractor 20 subtracts a feedback signal from the present input signal to produce a difference signal, and applies the difference signal to an integrator 30.
The integrator 30 functions to add the difference signal to the sum of previous difference signals so as to generate an integrated signal, and to supply the integrated signal to a comparator 43.
The comparator 43 is operative to coarsely quantize the integrated signal into one of two levels, and to supply the quantized signal to a latch 46. The latch 46 also receives a control signal at the sampling frequency f.sub.s from a clock generator (not shown) via input terminal 45, and is adapted to sample the quantized signal in response to the control signal and to supply the sampled value as an output D.sub.OUT to an output terminal 60 and to a digital to analog converter (DAC) 50. Alternatively, the comparator 43 finely quantizes the integrated signal to produce an output signal exhibiting more than two levels.
The DAC 50 receives the output signal D.sub.OUT and the control signal at the sampling frequency f.sub.s, and functions to convert the value D.sub.OUT to one of two output signal levels, and to supply the result as the feedback signal to the subtractor 20. The feedback ensures that the average value of the quantized signal tracks the average input.
As explained in James C. Candy et al., Oversampling Delta-Sigma Data Converters, IEEE Press, 1992, pages 2-7, for a first order delta sigma modulator, the rms noise n.sub.0 in the signal band f.sub.0 is given by: EQU n.sub.0.sup.1st order =e.sub.rms (.pi..sup.2 /3).sup.1/2 (2f.sub.0 /f.sub.s).sup.3/2 (eq. 1)
where e.sub.rms is the rms quantization error. Doubling the sampling frequency of a first order delta sigma converter decreases the in-band noise by 9 dB, corresponding to an increase in resolution of 1.5 bits.
The architecture of a first order delta sigma converter is fairly simple. Relatively imprecise circuit components can be used due to the presence of the feedback loop.
A second order delta sigma converter is shown in FIG. 2 as comprising subtractors 110, 130, integrators 120, 140, comparator 153, latch 156 and DAC 160. The second order delta sigma converter is generally similar to the first order delta sigma converter, except that the feedback signal is supplied to an "outer" subtractor 110 where it is combined with the input signal, and then integrated, before being applied to an "inner" subtractor 130.
An inner path comprising subtractor 130, integrator 140, comparator 153, latch 156 and DAC 160 serves to stabilize the system, and to determine the high frequency properties of the system. An outer path including subtractor 110 and integrator 120 dominates in determining the low frequency properties of the system.
For a second order delta sigma modulator, the rms noise n.sub.0 in the signal band f.sub.0 is given by: EQU n.sub.0.sup.2nd order =e.sub.rms (.pi..sup.4 /5).sup.1/2 (2f.sub.0 /f.sub.s).sup.5/2 (eq. 2)
Doubling the sampling frequency of a second order delta sigma converter decreases the in-band noise by 15 db, corresponding to an increase in resolution of 2.5 bits.
Relative to the first order delta sigma converter, the second order delta sigma converter is seen to reduce the quantization noise, permitting improved resolution. However, the second order delta sigma converter is less stable and less tolerant of component imprecision.
Delta sigma converters are generally used only with low frequency input signals, typically voice signals, due to the need for a high sampling frequency, specifically, a sampling rate up to several orders of magnitude higher than the Nyquist rate. For input signals of medium frequencies, components operating at an appropriately high sampling frequency are expensive. For input signals of high frequencies, components operating at an appropriately high sampling frequency are unavailable.
To achieve an effective sampling frequency of f.sub.s using components operating at a lower sampling frequency, it has been proposed to interleave two separate delta sigma converters each operating at f.sub.s /2, with the clock signals for the delta sigma converters being offset. Unfortunately, the oversampling ratio f.sub.s /f.sub.0 for each of these delta sigma converters is reduced by half, so the in-band noise for each of the delta sigma converters in the interleaved structure is increased by 9 dB relative to a single delta sigma converter operating at f.sub.s. Additionally, due to the noise from each delta sigma converter adding in quadrature, if uncorrelated, the in-band noise increases by an additional 3 dB. Overall, the noise increases by 12 dB for this scheme of interleaved delta sigma converters, corresponding to a reduction in resolution of 2 bits, relative to a single conventional delta sigma converter. Therefore, this proposed scheme is not effective.
Further, as known for example from EP734125 in the name of LeCroy Corporation, delta sigma converters are described below with reference to the figures, for the purpose of background information enabling the skilled man to put the technology into practice.
While that arrangement has many advantages as discussed in more detail throughout the description, various additional improvements are envisaged. In particular it is desired to reduce quantization noise and improve the signal to noise ratio yet further. Furthermore, the analog-to-digital converters in known arrangements such as those discussed above are typically of the "low-pass" type; that is, the circuit only responds to input signals containing frequencies below a certain cut-off frequency FC. Above this frequency the amplitude response to the circuit reduced in the digital representation of the input signal becomes inaccurate.